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As new Application specific System on Chip (SOC) with new IP’s are developed more bugs are discovered after fabrication. It is required to do functional changes to resolve these with minimal mask changes. This is because, At lower technology nodes mask cost is increasing exponentially, As shown in diagram below.

One of the methods that has been in use is to insert spare standard cells like NAND ,NOR ,D Flip Flop while designing SOC and use them later for doing functional changes. In this Article this concept is further extended.

Spare cells are inserted as a part Standard Cell based ASIC design methodology to allow any late Engineering Change Order (ECO) to be implemented by metal fixing.Traditionally, the Spare Cells that have been inserted comprises of AND, OR, inverter,NAND, NOR, MUX, Flip Flops. These cells have fixed functions or limited programmability. In this document a General purpose spare cell architecture is explored which can be programmed as 2/3 input combinational gates, Latch and Flip Flop.

Before diving into the Spare Cell architecture first consider the type of logic functions

that can be performed using 2:1 MUX.

Combinational gates that can be derived using 2:1 MUX are listed in Table 2.1

Till now we have seen logic functions derived using 2:1 MUX when two 2:1 MUX’s are cascased other combinational functions and FF can be obtained .

Some of the 3 input Combinational gates possible using 2 cascaded muxes are listed in Table 3.0

Architecture

Using this we can derive a general spare cell structure which can be logically programmed as 2/3 input NAND, NOR, AND etc gates as well as Latch and flip flop.A pin Description of Cell is described in Figure 3.2 In this architecture we can have a library of cells (

in our case 4 cells ) sharing the same layout and pins but metal1. Then we swap the master (i.e. programmation is done inside). Disadvantage of this is that cell functionality is fixed at the metal level.

Sequential mode

Benefits of this cell

With only slight increase in area as compared to FF a whole range of functions as described above can be performed.

Glossary

TI test scanin

TE test scanenable

D D input of Flop

CLK clock

CD active low asynchronous reset pin

Circuit -3 This is the description of spare cell used as latch.when used as a latch E=1.

Modes of Operation

Conventions used in diagrams

Dark lines indicate mode specific routings Light lines indicate routing present in all modes

Combinational mode

Circuit -1 This is the description of cell used (routing + basic cells ) when used in as 2/3 input combinational gate other than 3 input XOR.

By doing metal only changes Spare cell can be configured as various cells. The point to be taken care of is that metal 1 contacts should be same in all possible layouts. Pin mapping in various modes is described in Table 4.1. There are four possible layouts with respect to four possible modes .