System Structural Model

A system-level structural model is a block diagram or a netlist of system
components used for computation, storage, and communication. Processing
Elements (PEs) can be standard processors or custom-made processors. They
can also be application-specific processors or any other imported IPs or special functions
hardware components. Storage components are local or shared memories
which may also be included in other processing components. Communication
Elements (CE) are buses or routers possibly connected in a Network on-
Chip (NOC). If input-output protocols of some system component do not
match, we will need to insert Interface Components (IF) such as transducers,
bridges, arbiters, and interrupt controllers. Figure 1.8 shows a simple system
platform consisting of a CPU processor with a local memory, an IP component,
a specially-designed custom HW component, and the shared memory.
They are all connected through two buses, the CPU bus and IP bus.
Since CPU and IP buses use different protocols, a special IF unit (Bridge) is
included. The HW unit has the IF for the CPU bus protocol already built into
it. Since the CPU bus has CPU and HW components competing for the bus,
a special IF component (Arbiter) is added to grant bus access to one of the
requesting components.
A system structural model is generated from the given behavioral model by
the process called system synthesis.